This invention relates to a semiconductor memory such as a dynamic random-access memory (DRAM) or static random-access memory (SRAM), more particularly to a semiconductor memory having reduced peak operating current.
A semiconductor memory comprises a rectangular array of memory cells connected to pairs of complementary bit lines running in the column direction of the array. Sense amplifiers connected to the bit line pairs amplify small potential differences between the bit lines by allowing the bit lines to charge to the power supply potential or discharge to the ground potential. In prior-art semiconductor memory devices, a single switching element switches all the charge or discharge current from the sense amplifiers to or from a power supply or ground terminal.
In semiconductor memory devices with a large number of columns the sense amplifiers must charge or discharge a large number of bit lines, creating a considerable current surge that can in turn cause noise on the power supply or ground lines. A further problem is that parasitic resistance between the switching element and the power supply or ground impedes the current flow, thereby limiting the speed of operation of the memory. In effect, the voltage drop across the parasitic resistance alters the potential at a power supply or ground node adjacent to the switching element, leaving less electromotive force with which to charge or discharge the bit lines, thus lowering the current driving ability of the switching element. This tends to limit the practical size of the memory cell array.